Combining compilation and instruction set translation

ABSTRACT

In one embodiment of the present invention, a method includes translating instructions of a code portion from a first instruction set to a native instruction set; and disabling of translating the instructions when a compilation process is ready for execution.

BACKGROUND

[0001] Certain modern programming languages such as the JAVA™ language and C# execute in a managed runtime environment (MRTE) that provides automatic memory management and dynamic loading facilities, among other features. MRTEs dynamically load and execute code that is delivered in a portable format. Thus, that code must be converted into native instructions via interpretation or compilation. Code and other related data may be loaded from disk, read from a network stream, or synthesized in memory by an application. Methods include bytecodes to specify what to do when the method is invoked. Such bytecodes are machine independent and at a higher abstraction level than native instructions. Thus the MRTE converts bytecodes into native instructions.

[0002] A JAVA™ Virtual Machine (JVM) is a software layer used to execute JAVA™ bytecodes. Such JVMs can suffer from poor performance, including costly overhead. One manner of avoiding such problems is using just-in-time (JIT) compilation to implement a JVM.

[0003] Through JIT compilation, a bytecode method is translated into a native method on the fly, which may desirably remove interpretation overhead. However the JIT compilation is part of the total execution time of a JAVA™ program.

[0004] Current JIT compilation and instruction set translation do not operate smoothly together. Each approach has a benefit and a penalty. The compilation process cannot provide the system a benefit until the code is executed using an interpreter and past history on the system and software behavior is collected. Instruction set translation cannot benefit system behavior as efficiently as a compiled process because reordering of instructions and code sequences cannot be done by what is essentially a “look up table.”

[0005] A need thus exists to provide for better cooperation between compilation and instruction set translation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a flow diagram of a method in accordance with one embodiment of the present invention.

[0007]FIG. 2 is a block diagram of a portion of a processor in accordance with one embodiment of the present invention.

[0008]FIG. 3 is a block diagram of a wireless device with which embodiments of the invention may be used.

DETAILED DESCRIPTION

[0009] Referring now to FIG. 1, shown is a flow diagram of a method in accordance with one embodiment of the present invention. As shown in FIG. 1, a code portion may be fetched (block 110). In the embodiment of FIG. 1, the code portion may be fetched using a JVM. In one embodiment, the code portion may be a portion of JAVA™ code or NET code stored in memory, such as a flash memory. Next, the code portion may be analyzed to determine whether the code portion has been previously compiled (diamond 120). If so, the compiled code may be run (block 180) and control returns to block 110, at which point another portion of code is fetched.

[0010] As shown in the embodiment of FIG. 1, if the code portion has not been compiled, control next passes to block 130 in which bytecodes of the code portion are executed. During such execution, hardware updates profiling counters (block 140). The profiling counters will be discussed in more detail below. At the conclusion of executing the bytecodes for the range of the code portion, the profiling counters may be read (block 150).

[0011] Next, in one embodiment it may be determined whether to compile the bytecodes (diamond 160). The decision whether to compile on a given run may be based upon the values contained in the profile counters of different embodiments of the present invention. For example, based on one or more of the counters, it may be determined that the code portion is of sufficient importance (e.g., based on runtime or the like) to undergo compiling.

[0012] In one embodiment, software reading the counters (for example profiling middleware or firmware) may also determine whether to disable the profiling counters from further updating, as well as whether to disable instruction set translation (i.e., execution of bytecodes)(not shown in FIG. 1). For example, when a JIT compiler is ready for handoff, it may cause the profile counters and instruction set translation to be disabled. While the determination of whether to disable the counters may vary in different embodiments, in one embodiment the counters may be compared to predetermined parameters (i.e., thresholds). If the counters are not disabled, information stored in the counters (e.g., statistics) may be stored in memory for later retrieval and use in a later run of the same code portion. More so, instruction set translation continues.

[0013] In certain embodiments, profiling middleware may be used to collect data from the counters. In one such embodiment, middleware may track the counters for a specific number of high level code loops to determine basic behavior of a high level application using low level system hardware. In certain embodiments, a large number of executions of a code portion may be performed before sufficient information exists in the counters. For example, in certain embodiments, between approximately 500 and 2,000 runs may occur before the counters are disabled, and in one embodiment, approximately 1000 runs may occur.

[0014] If it is determined to compile the bytecodes, next a compilation process, such as a JIT compilation, may be performed on the code portion (block 170). As discussed, software (such as supervisor mode middleware) may cause disabling of the counters and instruction set translation at compilation handoff.

[0015] While the location of a JIT compiler may vary in one embodiment it may reside and execute from on chip memory. Alternately, such a compiler may reside in off chip memory in other embodiments. After compiling, the compiled code portion may be stored to memory along with an indication of its state as being compiled (block 170). Control then passes back to block 110 as discussed above. Alternately, if it was determined not to compile the code, control may pass directly from diamond 160 to block 110.

[0016] Referring now to FIG. 2, shown is a block diagram of a portion of a processor in accordance with one embodiment of the present invention. As shown in FIG. 2, processor 200 may include an instruction cache 210, translation unit 220, a core pipeline 230, and a counter array 240. In one embodiment, processor 200 may have a reduced instruction set computing (RISC) architecture, such as an architecture based on Advanced RISC Machines (ARM) architecture. For example, in one embodiment processor 200 may be a 32-bit version of an XSCALET™ processor available from Intel Corporation, Santa Clara, Calif.

[0017] As shown in FIG. 2, instruction cache 210 may be coupled to translation unit 220 to provide code 215 to the translation unit 220. As required, translation unit 220 may provide fetch instructions 218 to instruction cache 210 to obtain additional code 215.

[0018] In one embodiment, translation unit 220 may include a bytecode scheduler to perform instruction set translation (e.g., translate JAVA™ bytecodes to ARM instructions). Such ARM instructions 225 may be provided to core pipeline unit 230 which, in such an embodiment may be an ARM pipeline that executes ARM instructions. While the number of stages may vary, in certain embodiments a core pipeline having seven or more stages may be used. Translation unit 220 may also be coupled to counter array 240 to provide counter numbers thereto, as will be discussed in more detail below. More so, translation unit 220 may send exceptions 222 for instructions causing out of range memory locations.

[0019] During execution of instructions in core pipeline 230, certain data regarding execution of the instructions may be provided to one or more counters in counter array 240 via lines 235. Such data may include information regarding branches taken, branches not taken, mispredicted branches, a loop counter, bytecode type and the like. For example, counters on branch prediction and branch taken logic may be used to list what branches were predicted and which addresses were taken. In certain embodiments, counters for memory accesses or locations accessed may also be present. While shown in FIG. 2 as a counter array, it is to be understood that in different embodiments, counters need not be structured as an array. Further in other embodiments, profiling counters may be located elsewhere, for example, in translation unit 220.

[0020] As shown in FIG. 2, lines 245 may be used to provide traces from counter array 240 to translation unit 220. Such traces may be used to provide information to translation unit 220 regarding counts of variables used by translation unit 220. For example, translation unit 220 may include a set number of registers or variables within its logic to help it run stack operations efficiently. In such an embodiment, lines 245 may provide information regarding those variables. In particular, the information may include how many times they overflow as, in certain embodiments, only four to eight variables may be tracked in the logic, and the compiler would need to know if it should allocate variables to more registers directly for most efficient operation. As shown in FIG. 2, lines 228 may be used to provide counter number information to counter array 240 from translation unit 220.

[0021] In various embodiments of the present invention, a plurality of counters and disable switches therefor, along with certain software such as middleware may be provided. Such components may allow JIT compilation and instruction set translation to be combined such that the instruction set translation does not negate the ability of the compiler to profile the code behavior, but while the profiling is occurring, the high level code is directly executed rather than being emulated.

[0022] In certain embodiments, one counter may store information regarding variable names. In the JAVA™ language, such variable names may be equivalent to memory accesses in an object-oriented language such as C++. In one embodiment, counters may be present to count the number of times a code portion uses, for example, a group of variable names.

[0023] As discussed above, in various embodiments the profiling counters and instruction set translation may be disabled when compiling is to begin. As shown in FIG. 2, such disabling may be performed by software causing core pipeline 230 to turn off translation unit 220 via a switch signal sent on line 233 and to turn off counter array 240 via a switch signal sent via lines 235. In different embodiments, such switches may be located inside or outside of counter array 240 and translation unit 220, respectively.

[0024] Embodiments of the present invention may be implemented in code and may be stored on a storage medium having stored thereon instructions which can be used to program a system, such as a wireless device to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any type of media suitable for storing electronic instructions.

[0025]FIG. 3 is a block diagram of a wireless device with which embodiments of the invention may be used. As shown in FIG. 3, in one embodiment wireless device 500 includes a processor 510, which may include a general-purpose or special-purpose processor such as a microprocessor, microcontroller, application specific integrated circuit (ASIC), a programmable gate array (PGA), and the like. Processor 510 may be coupled to a digital signal processor (DSP) 530 via an internal bus 520. In turn, DSP 530 may be coupled to a flash memory 540.

[0026] As shown in FIG. 3, microprocessor device 510 may also be coupled to a peripheral bus interface 550 and a peripheral bus 560. While many devices may be coupled to peripheral bus 560, shown in FIG. 3 is a wireless interface 570 which is in turn coupled to an antenna 580. In various embodiments antenna 580 may be a dipole antenna, helical antenna, global system for mobile communication (GSM) or another such antenna.

[0027] Although the description makes reference to specific components of device 500, it is contemplated that numerous modifications and variations of the described and illustrated embodiments may be possible.

[0028] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention. 

What is claimed is:
 1. A method comprising: executing bytecodes; and collecting hardware profiling data regarding the bytecodes.
 2. The method of claim 1, further comprising interpreting the hardware profiling data.
 3. The method of claim 2, further comprising determining whether to compile the bytecodes based on the hardware profiling data.
 4. The method of claim 1, wherein the hardware profiling data comprises a count of variable names.
 5. The method of claim 1, further comprising obtaining the bytecodes in a managed runtime environment.
 6. The method of claim 1, further comprising disabling collecting the hardware profiling data upon meeting a predetermined threshold.
 7. The method of claim 1, further comprising disabling executing the bytecodes upon initiation of a compilation process.
 8. A method comprising: translating instructions of a code portion from a first instruction set to a native instruction set; and disabling of the translating the instructions if a compilation process is ready for execution.
 9. The method of claim 8, wherein the first instruction set comprises bytecodes.
 10. The method of claim 8, further comprising compiling the code portion.
 11. The method of claim 10, wherein compiling the code portion comprises performing just-in-time compilation.
 12. The method of claim 8, wherein the disabling is based on a value stored in at least one profile counter.
 13. The method of claim 12, further comprising disabling the at least one profile counter when the compilation process is ready for execution.
 14. An apparatus comprising: a plurality of hardware counters coupled to a processing unit to collect information regarding instructions executed in the processing unit.
 15. The apparatus of claim 14, further comprising a switch coupled to disable the plurality of hardware counters.
 16. The apparatus of claim 14, further comprising a memory coupled to the plurality of hardware counters.
 17. The apparatus of claim 14, further comprising a translation unit to convert bytecodes into the instructions.
 18. The apparatus of claim 17, wherein the translation unit is disabled when a compilation process occurs.
 19. An article comprising a machine-readable storage medium containing instructions that if executed enable a system to: execute bytecodes; and collect hardware profiling data regarding the bytecodes.
 20. The article of claim 19, further comprising instructions that if executed enable the system to interpret the hardware profiling data.
 21. The article of claim 20, further comprising instructions that if executed enable the system to determine whether to compile the bytecodes based on the hardware profiling data.
 22. The article of claim 19, further comprising instructions that if executed enable the system to disable collecting the hardware profiling data upon meeting a predetermined threshold.
 23. A system comprising: at least one storage device to store code to translate instructions of a code portion from a first instruction set to a native instruction set, and to disable translating the instructions when a compilation process is ready for execution; and a dipole antenna coupled to the at least one storage device.
 24. The system of claim 23, further comprising a processor coupled to the at least one storage device to execute the code and a plurality of hardware counters coupled to the processor.
 25. The system of claim 24, wherein the processor includes a translation unit to translate the instructions.
 26. The system of claim 25, wherein the translation unit is disabled when the compilation process is ready for execution. 